Technical Design Manager - FPGA Verification

Perfectus Technology is looking for an experienced Technical Design Manager to lead verification and hardware design projects. This role involves working with advanced FPGA technologies and high-speed communication protocols in a fast-paced environment.

• Manage technical design and verification processes using C/C++ and Verilog HDL
• Implement and map PCI-Express core interfaces on Xilinx Virtex-II FPGA systems
• Synthesize designs using Synplify tools for RapidIO, Gigabit Ethernet, or SONET domains
• Perform rigorous timing analysis using Pearl and Cadence Buildgates tools
• Oversee hardware mapping and system-level verification according to technical protocols

• Master's degree (M.S.) or equivalent in Electronic Engineering or a related field
• Minimum 3 years of professional experience in RTL design and hardware verification
• Proven expertise in Verilog HDL, VCS, Pearl timing analysis, and Cadence Buildgates
• Practical experience with Xilinx Virtex-II FPGA and Synplify synthesis tools
• Solid understanding of Gigabit Ethernet, RapidIO, or SONET communication protocols

• Opportunity to work in Bengaluru, the hub of India's semiconductor industry
• Professional growth in high-end VLSI design and FPGA implementation
• Exposure to international projects with potential relocation opportunities within the USA
• Competitive professional environment at a highly-rated technology company

• Job entails deep technical involvement in mapping and synthesis tasks
• Relocation within USA is a possible future prospect for qualified candidates
• Applicants must mention Job Code – TDM in the subject line of their email